General Info

Instructor: Chixiao Chen, PhD.

Email: cxchen@fudan.edu.cn

Location: H2218 @ Fudan University, Handan Campus

(Online Teaching until on-campus teaching is allowed )

Time:  Thursday Evening 

Prerequisite: Verilog  ( Digital Logic, and experiences by verilog/sv/chiesel/…)

[选修本课程的同学须有Verilog经验，熟悉《数字逻辑》的相关内容]

Score: Homework Assignement (15% x 4)+ Final Project/Presentation (40%)

Previous Course Site: Computer and AI Architecture @ 2019 Spring

Announcement

Course Calendar and Materials

** Please ignore the unsafe notification and go the external video link.

Week  Date  wawswwaLecturewwwsawa  Slides   Video  HmWrk
1 3/5 Introduction (Overview, birth of microprocessors, and discovery of neural network ) Lec01 Part1 Part2 Part3
2 3/12 ISA (Dark Silicon, ISA and an ISA example for NN ) Lec02

Part1 Part2
Part3
3 3/19 Verilog and RISC hardware organization Lec03

Part1
Part2

HW1
4/2 Due
4 3/26 Pipeline, Custom-Pipeline and super-scalar arch  Lec04

Part1
Part2
Part3
5 Multi-thread, GPU arch
6 Review on DNN, Winograd
7 CGRA, FPGA arch
8 Dataflow optimization
9 DNN Quantization
10 Computer-in-Memory
11 RISC-V Instruction Set
12 Single Cycle RV32I arch
13 Pipeline RV32I arch
14 Hazards
15 Final Project (No Class)
16 Final Presentation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

References

The instructor thanks the contributors of the following materials

  1. TingTing Hwang, Computer Architecture, National Taiwan Tsinghua University. 
  2. CS231n, Convolution Neural Network, Stanford University.
  3. Krste Asanović, CS252, Graduate Computer Architecture, UC Berkeley.
  4. CS61c, Great Ideas in Computer Architecture, UC Berkeley
  5. Vivienne Sze, Tutorial on Hardware Accelerators for DNN, MIT.
  6. Haozhe Zhu, Verilog Training Material.